(1) Field of the Invention
The present invention generally relates to PLL frequency synthesizers, and more particularly to a PLL frequency synthesizer having an improved circuit arrangement for reducing power consumed in the PLL frequency synthesizer.
(2) Description of the Prior Art
Recently, PLL (Phase-Locked Loop) frequency synthesizers have been used in various mobile communication devices, such as portable telephone sets and cordless telephone sets. It is desired that such mobile communication devices are compact and light, and particularly consume a small amount of energy. In general, mobile communications devices utilize PLL frequency synthesizers. In order to satisfy the above-mentioned requirements, it is required that the PLL frequency synthesizers consume a small amount of energy.
The mobile communication device has a communication mode and a standby mode. In general, the mobile communication device is maintained in the standby mode for a long time. In the standby mode, the mobile communication device does not communicate with the other communication device except that a control communication is executed between the mobile communication device and a control office at predetermined intervals. If electricity is continuously supplied to the mobile communication device in the standby mode, electricity is consumed wastefully. With this in mind, electricity is intermittently supplied to the mobile communication device at predetermined intervals as necessary to execute the control communications. With this arrangement, it is possible to save a considerable amount of energy. In order to execute power supply intermittently, it is necessary to operate the PLL frequency synthesizer intermittently.
FIG. 1 is a block diagram of a conventional PLL frequency synthesizer. As shown, the PLL frequency synthesizer is composed of a crystal oscillator circuit 1, a reference counter 2, a prescaler 3, a programmable counter 4, a phase comparator 5, a lowpass filter (LPF) 6, and a voltage-controlled oscillator (VCO) 7. A PLL circuit 8 is composed of the crystal oscillator circuit 1, the reference counter 2, the prescaler 3, the programmable counter 4 and the phase comparator 5.
As shown in FIG. 2, a switch 9 is provided between a power source Vcc, such as a battery, and the PLL circuit 8. The switch 9 is controlled by a power save signal PS, which has, for example, a high level in the communication mode, and a low level in the standby mode. The level of the power save signal PS periodically changes. Thereby, electricity from the power source Vcc is intermittently supplied to the PLL circuit 8.
However, it is difficult to establish correct and definite operation of the PLL frequency synthesizer. In order to improve the operation of the PLL frequency synthesizer, it may be possible to use a circuit configuration shown in FIG. 3. The power save signal PS is input to the crystal oscillator circuit 1, the prescaler 3 and the voltage-controlled oscillator 7. The crystal oscillator 1 stops oscillating in the standby mode in response to the power save signal PS. The prescaler 3 does not transfer the signal from the voltage-controlled oscillator 7 to the programmable counter 4 in the standby mode. An initial phase detection circuit 10 and a buffer 11 are added to the configuration shown in FIG. 1, as shown in FIG. 3.
The initial phase detection circuit 10 inputs the signal from the prescaler 3 and the signal from the crystal oscillator circuit 1 via the buffer circuit in response to the high level of the power save signal PS. When the difference between the rise timing of the signal from the prescaler 3 and the rise timing of the signal from the crystal oscillator circuit 1 falls within a predetermined range, the initial phase detection circuit 10 generates an in-phase detection signal, which is input to the counters 2 and 4, and the phase comparator 5. The counters 2 and 4, and the phase comparator 5 do not receive the respective input signals until the power save signal PS switches to the high level from the low level and the in-phase detection signal is received.
When the power save signal PS has the low level, the crystal oscillator circuit 1 does not execute the oscillation operation, and the prescaler 3 is switched to a no-signal state where the prescaler 3 cuts off the signal from the voltage-controlled oscillator 7. Hence, the reference counter 2 and the programmable counter 4 do not receive any signal although they receive electricity. In general, the prescaler 3 is composed of CMOS (Complementary Metal Oxide Semiconductor) transistors. Thus, energy is not consumed in the prescaler 3 in the no-signal state. Since each of the reference counter 2 and the programmable counter 4 is also composed of CMOS transistors, they do not consume energy in the no-signal state. In addition, data in the counters 2 and 4 is maintained without being destroyed since they are supplied with electricity.
The phase comparator 5 is composed of CMOS transistors, and receives signals from the counters 2 and 4 indicating that the frequency is zero in the no-signal state. In this state, the phase comparator 5 does not consume energy. Further, the phase comparator 5 is maintained in a high-impedance state when the power save signal PS has the low level. The oscillation frequency of the voltage-controlled oscillator 7 does not deviate from a previously locked frequency when the power supply to the phase comparator 5 which is in the high-impedance state is stopped for a very short time, because a control voltage applied to the voltage-controlled oscillator 7 and obtained before the power save signal PS switches to the low level is maintained in the lowpass filter 6. When the power save signal PS switches from the low level to the high level, the crystal oscillator circuit 1 starts to oscillate, and the signal from the voltage-controlled oscillator 7 is input to the prescaler 3. At this time, the output signals of the crystal oscillator circuit 1 and the prescaler 3 are input to the counters 2 and 4, respectively, while the in-phase detection signal has not yet been input to the counters 2 and 4. Hence, the counters 2 and 4 and the phase comparator 5 do not start to operate at this time.
When the initial phase detection circuit 10 detects the in-phase state where the difference between the rise timings of the signals from the crystal oscillator circuit 1 and the prescaler 3 falls within the predetermined range, the in-phase detection signal is applied to the counters 2 and 4 and the phase comparator 5. In response to the in-phase detection signal, the counters 2 and 4 and the phase comparator 5 receive the respective input signals and start to operate.
With the above-mentioned arrangement, it becomes possible to reduce energy consumed in the PLL frequency circuit and to start to operate the PLL frequency circuit after the phase is locked.
The prescaler 3 composed of CMOS transistors is capable of handling a high-frequency signal having a frequency equal to or higher than, for example, 50 MHz. In order to obtain such a high-frequency signal from the PLL frequency synthesizer, it is necessary to form the prescaler 3 with bipolar transistors. It should be noted that the prescaler 3 including bipolar transistors consumes energy even when it does not receive any signal since current continuously flows through the bipolar transistors. In order to intermittently operate the prescaler 3 including bipolar transistors, it is necessary to completely cut off current passing through the bipolar transistors.
However, this has a disadvantage in that data stored in an internal latch of the prescaler 3 is destroyed because the current passing through the bipolar transistors is temporarily cut off. As a result, the signal which is output by the prescaler 3 in the initial state has a frequency which varies greatly. Even if the counters 2 and 4 and the phase comparator 5 start to operate in response to the in-phase detection signal, the phase comparator 5 compares the signals having varying frequencies. Hence, even though the phases of the signals input to the phase comparator 5 are initially coincident with each other, it becomes impossible to accurately execute the phase comparing operation after the initial state. As a result, the PLL frequency synthesizer has an unstable state, and it takes a long time to lock the phase of the PLL frequency synthesizer.
When the prescaler 3 is released from the current cutoff state, all current sources of the bipolar circuit of the prescaler 3 start to operate, and thus voltages at nodes of the prescaler 3 vary. This causes ringings to occur in the voltage waveforms.